PCB Test Points and Test Tole Design
Posted: May 14, 2022
By: Bonnie
In the large production of SMT, in order to ensure quality and reduce costs, online testing is indispensable. In order to ensure the smooth progress of the test, the PCB design should take into account the design of the test points and test holes (electrical connection holes for electrical performance testing of PCB and PCB components).
(1) Contact reliability test design. In principle, the test points should be placed on the same side, and the dispersion should be uniform. The test pad has a pad diameter of 09mm ~ 1.0mm and is matched with the relevant test pin. The center of the test point should fall on the grid, and note that it should not be designed within 5mm of the edge of the board. The center distance between adjacent test points is not less than 1.46mm.
No other components should be designed between the test points. The distance between the test points and the component pads should be no less than 1mm to prevent short circuit between the components or test points. Note that the test points cannot be coated with any insulation layer.
In principle, the test hole can be replaced by a process hole, but the test hole should still be designed on the daughter board for the slab test of the panel.
(2) Electrical reliability test design, all electrical nodes should provide test points, that is, test points should cover all I / 0, power ground and return signals, each IC should have power and ground test points, If the device has more than one power supply and ground, test points should be added separately. The power and ground of one integrated block should be placed within 2.54mm.
The IC control line cannot be directly connected to the power supply, ground or common resistor. VLSI and ASIC devices with boundary-scan devices should be added as auxiliary test points for boundary scan functions, such as clock, mode, data serial input/output, and reset, to achieve internal functional logic that can test the device itself.
No other components should be designed between the test points. The distance between the test points and the component pads should be no less than 1mm to prevent short circuit between the components or test points. Note that the test points cannot be coated with any insulation layer.
In principle, the test hole can be replaced by a process hole, but the test hole should still be designed on the daughter board for the slab test of the panel.
(2) Electrical reliability test design, all electrical nodes should provide test points, that is, test points should cover all I / 0, power ground and return signals, each IC should have power and ground test points, If the device has more than one power supply and ground, test points should be added separately. The power and ground of one integrated block should be placed within 2.54mm.
The IC control line cannot be directly connected to the power supply, ground or common resistor. VLSI and ASIC devices with boundary-scan devices should be added as auxiliary test points for boundary scan functions, such as clock, mode, data serial input/output, and reset, to achieve internal functional logic that can test the device itself.
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