The components must be isolated from the outside to prevent the impurities in the air from corroding the chip circuit and causing the electrical performance to decline. On the other hand, the packaged chip is also easier to install and transport. The quality of the packaging technology also directly affects the performance of the chip itself and the design and manufacturing of the PCB (printed circuit board) connected to it, so it is crucial.

An important indicator of whether a component packaging technology is advanced or not is the ratio of chip area to package area. The closer this ratio is to 1, the better. Main considerations when packaging:
1. The ratio of chip area to package area is as close to 1: 1 as possible to improve package efficiency;
2. The pins should be as short as possible to reduce the delay, and the distance between the pins should be as far as possible to ensure that they do not interfere with each other and improve performance;
3. Based on heat dissipation requirements, the thinner the package, the better.

1. Packages are mainly divided into DIP dual in-line and SMD chip packages.

In terms of structure, the package experienced the earliest transistor TO (such as TO-89, TO92) packaging and developed to a dual in-line package. Subsequently, PHILIP developed a small SOP package. Later, SOJ (J-type) was gradually derived. Lead small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (reduced size SOP), TSSOP (thin reduced size SOP), SOT (small outline transistor), SOIC (small outline Integrated circuits) and so on.
In terms of material and media, including metals, ceramics, plastics, and plastics, many circuits that require high-intensity working conditions, such as military and aerospace grades, still have a large number of metal packages.

The encapsulation has gone through the following development processes:

Structural aspects: TO-> DIP-> PLCC-> QFP-> BGA-> CSP;
Materials: metal, ceramics-> ceramics, plastics-> plastics;
Pin shape: long lead straight insertion-> short lead or leadless mounting-> spherical bump;
Assembly method: through-hole insertion-> surface assembly-> direct installation

2. Specific package form

2.1 SOP / SOIC package
SOP is the abbreviation of Small Outline Package, that is, small outline package. SOP packaging technology was successfully developed by Philip from 1968 to 1969. Later, it gradually derived SOJ (J-pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (reduced size) SOP), TSSOP (Thin Reduced SOP), SOT (Small Outline Transistor), SOIC (Small Outline Integrated Circuit), etc.

2.2 DIP package
DIP is the abbreviation of Double In-line Package. One of the plug-in packages, the pins are drawn from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its applications include standard logic ICs, memory LSIs, and microcomputer circuits.

2.3 PLCC package
PLCC is the abbreviation of Plastic Leaded Chip Carrier. PLCC packaging method, the shape is square, 32-pin package, there are pins around, the size is much smaller than the DIP package. The PLCC package is suitable for mounting and wiring on the PCB using SMT surface mounting technology, and has the advantages of small size and high reliability.

2.4 TQFP package
TQFP is a thin plastic package with four corner flat packages. The four-sided flat package (TQFP) process can effectively use space, thereby reducing the space requirements of printed circuit boards. Due to the reduced height and volume, this packaging process is well-suited for space-critical applications such as PCMCIA cards and network devices. Almost all ALTERA CPLD / FPGAs are available in TQFP packages.

2.5 PQFP package
PQFP is a plastic four-corner flat package. The distance between the pins of the PQFP package is very small, and the pins are very thin. Generally, large-scale or ultra-large-scale integrated circuits use this package, and the number of pins is generally more than 100.

2.6 TSOP package
TSOP, that is, thin small size package. A typical feature of TSOP memory packaging technology is to make pins around the packaged chip. TSOP is suitable for mounting wiring on PCBs (printed circuit boards) using SMT technology (surface mount technology). When the TSOP package dimensions are small, the parasitic parameters (when the current changes greatly, causing output voltage disturbances) are reduced, which is suitable for high-frequency applications. It is easy to operate and has high reliability.

2.7 BGA Package
BGA, that is, ball grid array package. The memory packaged with BGA technology can increase the memory capacity by two to three times while the volume is unchanged. Compared with TSOP, BGA has a smaller size, better heat dissipation performance and electrical performance. BGA packaging technology has greatly improved the storage capacity per square inch. Memory products using BGA packaging technology have only one-third the volume of TSOP packages at the same capacity. In addition, compared with traditional TSOP packaging methods, BGA packaging There are more rapid and effective cooling methods.
The BGA package's I / O terminals are distributed under the package in a circular or columnar solder joint in an array. The advantage of BGA technology is that although the number of I / O pins has increased, the pin pitch has not decreased but increased. Improved assembly yield; although its power consumption has increased, BGA can be soldered using a controlled collapse chip method, which can improve its electrical and thermal performance; thickness and weight are reduced compared to previous packaging technologies; parasitic parameters are reduced, The signal transmission delay is small, and the frequency of use is greatly increased; assembly can be coplanar welding, high reliability.

3. Information on packaging naming rules of some brand

3.1 MAXIM
The MAXIM prefix is "MAX". DALLAS starts with "DS". MAX ××× or MAX ××××
Explanation:
1). Suffixes CSA and CWA, where C is ordinary, S is surface mount, and W is wide body surface mount.
2). The suffix CWI indicates wide body surface mount, EEWI wide body industrial level surface mount, and the suffix MJA or 883 is military grade.
3). CPA, BCPI, BCPP, CPP, CCPP, CPE, CPD, ACPA suffixes are all ordinary in-line.
For example MAX202CPE, CPE common ECPE with antistatic protection
MAX202EEPE industrial-grade antistatic protection (-45 ℃ -85 ℃), which means E refers to the antistatic protection MAXIM number arrangement classification
1-prefix simulator;
2-prefix filter;
3-head multi-way switch;
4-word head amplifier;
5-digit digital-to-analog converter;
6-head voltage reference;
7-head voltage conversion;
8-head reset;
9-head comparator;
DALLAS naming rules
For example DS1210N.S. DS1225Y-100IND
N = Industrial Grade S = Surface Mount Wide Body MCG = DIP Seal Z = Surface Mount Wide Body MNG = DIP Industrial Grade;
IND = Industrial grade QCG = PLCC seal Q = QFP;

3.2 ADI
Most AD products start with "AD" and "ADV", and also have "OP" or "REF", "AMP", "SMP", "SSM", "TMP", "TMS", etc.
Description of the suffix:
1). J in the suffix indicates civilian products (0-70 ° C), N indicates ordinary plastic packaging, and R in the suffix indicates surface sticker.
2). D or Q in the suffix indicates ceramic seal, industrial grade (45 ℃ -85 ℃). H in the suffix indicates a round cap.
3). SD or 883 is a military product in the suffix.
For example: JN DIP package JR surface mount JD DIP pottery seal

3.3 BB
BB product naming rules:
Prefix ADS analog device Suffix U surface mount P is DIP package with B for industrial grade prefix INA, XTR, PGA, etc. indicates high precision op amp Suffix U surface mount P stands for DIP PA stands for high precision

3.4 INTEL
INTEL product naming rules:
N80C196 series are all single chip computers;
Prefix: N = PLCC package T = Industrial S = TQFP package P = DIP package;
KC20 clock frequency KB clock frequency MC represents 84 angles;
Example: TE28F640J3A-120 flash memory TE = TSOP DA = SSOP E = TSOP.

3.5 ISSI
Start with "IS"
For example: IS61C IS61LV 4 × means DRAM 6 × means SRAM 9 × means EEPROM;
Package: PL = PLCC PQ = PQFP T = TSOP TQ = TQFP;

3.6 LINEAR
Prefixed with product name
LTC1051CS CS means surface mount;
LTC1051CN8 ** indicates * IP package 8 pins;
The suffix C is for civilian use and I is for industrial use.

3.7 IDT
IDT products generally start with IDT
Description of the suffix:
1). TP in the suffix is a narrow body DIP
2). P is a widebody DIP in the suffix
3). J belongs to PLCC in the suffix
For example: IDT7134SA55P is a DIP package
IDT7132SA55J is PLCC
IDT7206L25TP is DIP

3.8 NS
The product part of NS starts with LM and LF
LM324N 3 prefix represents folk products with N round cap;
LM224N 2 prefix represents industrial grade with N plastic package;

LM124J 1 prefix represents military products with J Tao Feng.